using io as clk inputs

Hi,

I am not a pro designer but here is what i think : for example Cyclone IV handbook states that "The general I/O pins cannot drive the PLL clock input pins". This means that you will not get ability to use PLL and fine tune phase shift on your clock and probably you will fail to meet timing requirements on high speed interfaces. But if you plan to clock some low speed SDR interfaces i think it will work (I tried this and it worked).