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Altera_Forum
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14 years ago

Using half of DDR2 SO-DIMM

I want to use 1/2 of a DDR2 so-dimm module with 32 bit wide DDR2 interface to Cyclone II. Has anyone done this? I believe this will work, provided I properly terminate the unused chips on the module. Electrically, it will be like I have the 32 bit wide DDR chips on my board. I don't have enough pins to interface the full 64 bits, and my bandwidth is fine with just the 32.

I'm using the DQ0-31 pins, DQS0-4, DM0-3, CK0 pair, CS0, and the address/strobe pins. I'm not using the DQ32-63, DQS5-7, DM4-7, CK1, ODT1, CS1.

Can anyone think of a reason this can't work? Or confirm that they have seen it work?

What is the proper way to terminate the unused pins? Is it enough to just de-assert the CS1 pin?

Thanks!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The most interesting questions is how the RAM chips act power supply-wise when not being clocked. Will they stay idle or possibly draw excessive current? Honestly speaking, I'm not able to predict this from the datasheets.

    Alternatively, you may want to explicitely set the unused chips to power down mode, which would require clocking it at least temporarily. But perhaps you can find information about behaviour of unclocked RAM chips in any data sheet or application note.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I don't know what chips would do without any clock. I presume they would draw normal quiescent current. I've seen a number of embedded processor boards with DRAM chips, where the DRAM controller isn't turned on until enabled by software. And in some applications where the DRAM isn't needed, it may not ever be enabled. So, I don't think there is any problem with excessive current draw. Of course, this is only anecdotal.

    My main concern is making sure they don't draw excessive current (latch up, or floating input).
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    CMOS chips have no normal quiescent current, I think. Another point is, that DDR2 RAMs incorporate a clock processing PLL, so it's no easy to decide what they do without an input clock.

    I agree, that driving defined levels to all control inputs can be a starting point. The said power option still exists, but involves additional effort.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I got a response from Micron's technical department. They said there is no problem leaving the pins of the unused chips floating.