Honored Contributor
Honored ContributorHi Hans,
--- Quote Start --- First of all, let me thank you for your reply. --- Quote End --- You're welcome. --- Quote Start --- I have been working on this for the last few days making incremental progress. After some head-scratching I think I am 95% done, only one final issue to resolve (I hope). So far I have been able to: 1. Controlling the nConfig, so it can be asserted (and deasserted) to start the configuration. 2. Load the file.rbf file and send it to the FPGA, (256K in 1-2 seconds), Config_Done goes high. 3. I included logic in the FPGA-Hardware image which drives a pin out at 1 KHz (I can see it on Oscilloscope) so I know the image is loaded. --- Quote End --- Ok, so up until here we are talking about FPGA *hardware*. --- Quote Start --- 4. C-code toggles another pin. I do see it working when JTAG is used to load FPGA, however, I do not see it when FT2232H is loading the FPGA (JTAG removed) --- Quote End --- Just to be clear: for JTAG you're using a USB-Blaster, and the FTDI is being used for Passive Serial? They are identical as far as downloading hardware is concerned. There can be a subtle difference when dealing with software. I believe (and may be wrong) that if you include a JTAG UART in the design, and you are *not* using JTAG, then you might be able to break your design. So, what other software components are in your system? Anything JTAG related could be removed to test this theory, and then added back in later. --- Quote Start --- 5. Being able to observe the Init_done pin would be great. However, it is used for LVDS so I do not think it can be used (not sure). --- Quote End --- You don't need INIT_DONE. You've confirmed with your 1kHz pin toggling that the FPGA is configured. Now you are onto software debugging. --- Quote Start --- So I am wondering: Do I need to assert (and deassert) the reset line to the FPGA after it has been loaded? --- Quote End --- It totally depends on where that reset line is. The answer could be as simple as "press the reset button". But if it was that simple, you would not be asking :) What reset line are you referring to? Note that technically you do not have to have a reset - when the FPGA configures all of the registers are in a well-defined state (I personally prefer having a reset source though). Depending on whether any of the programming pins you have access to (via FTDI) can be reconfigured as an I/O pin after programming, you could use it as a reset to your design, eg., assert it to see the 1kHz signal stop and then deassert it to see the signal toggling again. Cheers, Dave
