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I am using a 12-bit ADC
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Ok. FPGA multipliers increment in steps of 9-bits, so you'll likely end up using an 18-bit multiplier.
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Also, given I would need around 44 multipliers
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The filter has 44 coefficients. This does not mean 44 multipliers. For a start, the coefficients are symmetric, so that halves the number of multipliers you would use if you implemented an FIR at the same rate as the ADC data. However, once you are decimating data, you are in "multi-rate" territory, where your FIR filter can reuse an FPGA DSP block operating at a higher frequency than your data rate.
Do a little more work figuring out the filter logic first, and then look at the FPGA.
Cheers,
Dave
Honored Contributor
