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I would like decide on a FPGA family and size for this.
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I think a Cyclone IV would probably work. The resources required depend on your ADC bit-width and the stop-band rejection you need to achieve, since that determines the multiplier bit-width.
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I had FDAtool simulating a few different filter designs. As you discussed, if I used a decimate-by-4 filter it would requires 44 coefficients. Is there a method that relates the filter coefficients to the FPGA resources required?
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It depends on the filter structure. Given that your decimated data rate is a lot lower than your FPGA clock rate, fewer than 44 multipliers will be used. Altera has an FIR compiler that you can try to use, otherwise try and implement a few filters yourself. You can always get one example working, use that to select the FPGA, and then "optimize" the implementation later.
Cheers,
Dave
Honored Contributor
