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Altera_Forum
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12 years ago

Using CPLDs as a dedicated DDC

Hi, The have an ADC sampling at 37.4MSps and I want to fed this data into a DSP for real-time baseband processing. However, I need an interface between the ADC and DSP to digitally down convert...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Great examples! and thanks for the references.

I like the idea of implementing all DDC DSP in a FPGA ie complex-valued baseband (mixing fs/4 = 9.35MHz) and decimation filter (by 4). I would like decide on a FPGA family and size for this.

I had FDAtool simulating a few different filter designs. As you discussed, if I used a decimate-by-4 filter it would requires 44 coefficients. Is there a method that relates the filter coefficients to the FPGA resources required?

Cheers,

Les.