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Altera_Forum
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12 years ago

Using CPLDs as a dedicated DDC

Hi, The have an ADC sampling at 37.4MSps and I want to fed this data into a DSP for real-time baseband processing. However, I need an interface between the ADC and DSP to digitally down convert...
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Altera_Forum
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12 years ago

Hey Les,

Here's an example of what is feasible (calculated using MATLAB's FDAtool);

1) ADC input Fs = 37.4MSps, 16-bit samples

2) Decimation-by-2

Low-pass filter passband = DC to 3MHz, 0.1dB passband ripple, stopband at 37.4/2-3 = 15.7MHz, 90dB stopband rejection.

9 filter coefficients required. The four either side of the center are identical, so there are 5 unique coefficients.

3) Decimation-by-4

Low-pass filter passband = DC to 3MHz, 0.1dB passband ripple, stopband at 37.4/4-3 = 6.35MHz, 90dB stopband rejection.

44 coefficients required. The coefficients are symmetric, so 22 unique values.

Because FPGAs can operate at >100MHz, both of these filters can probably be implemented using only one or two hardware multipliers. Implementing this type of DSP using an FPGA makes life easier, since it has memory to store the ADC samples, while the multiplier operates at a higher clock frequency and processes the data.

Cheers,

Dave