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Sorry, yes I was meaning to use +1 0 -1 then do a Hilbert transform to obtain Q.
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Hilbert transforms don't always have a good frequency response across the whole band, however, in your case, your signal bandwidth is fairly small compared to your sampled bandwidth, so it might be ok. I'd compare both methods and select the one that works best.
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Using a complex-valued exponential looks like a very handy method. Do you know of any good references on this method?
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Sure, look at these (there's references to books etc)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104slides_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104code_hawkins.zip --- Quote Start ---
I'm not sure what you mean by "that you saturate your most-negative value to -2^(B-1)+1, which is the negative of the most positive value +2^(B-1)-1, then you can simply rearrange the real-valued data into a complex-valued data stream."
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A B-bit number in 2's compliment format has the range -2^(B-1) to 2^(B-1)-1, eg., B = 8-bits can represent -128 to 127. If you demodulate that using +/-1 and +/-j, what do you do with -(-128) = +128? This is a 9-bit 2's compliment number, so negation has caused an unnecessary bit-growth of 1-bit. A "better" solution is to look at the ADC samples and replace every sample equal to -128 with -127. That results in an ADC data stream that is "signed symmetric", and allows you to simply flip the sign in the demodulation, eg., -(-127) = +127, without any bit-growth. This does not increase quantization noise, since you have already saturated the most-positive signal to +127.
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The bandwidth of interest is +/- 3MHz. Also, the channel of interest has a 25KHz BW. I'm thinking once the +/-3MHz is at baseband I can then filtering and FM demodulate the 25KHz channel in the DSP.
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Then depending on whether you decide to just preserve the channel, or the full 3MHz, your FIR filter can have a very slow transition, so it will require fewer coefficients, and be simpler to implement. The filter will also have less bit-growth, so the data width going to the DSP will not get too large.
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How do I identify the maximum amount I can decimate by?
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By designing the filter :) Seriously though, use a package like MATLAB or Octave, decide what your transition bandwidth, passband ripple, and stop-band requirements are, and design a couple of filters.
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If I can work how much resources used for this then maybe I can gauge how big FPGA/CPLD I would need.
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First determine what the maximum sustained transfer rate from your FPGA to CPLD is; that will be your system bottleneck.
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The core processor of the DSP is 400MHz - I think it would be nice to decimate as much as possible to increase the instructions per cycle in the DSP. but as you say decimating "as much as is needed", I can use less resources in the CPLD/FPGA. This will require optimization methods.
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It depends on whether you like writing software or hardware :) Personally I would "optimize" to have the FPGA do it all. Then there is no ambiguity in performance.
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Do you have any suggestion on selecting a FPGA for the DDC? Many thanks in advance.
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The references above will help get you started.
Don't be afraid to start coding. Write some MATLAB/Octave code. Write some HDL code and some DSP code. Get an idea of what the performance of each is, and then you'll have a much better sense of where you want the code to run.
Cheers,
Dave
Honored Contributor
