Honored Contributor
Honored ContributorThanks for the great feedback!
Sorry, yes I was meaning to use +1 0 -1 then do a Hilbert transform to obtain Q. Using a complex-valued exponential looks like a very handy method. Do you know of any good references on this method? I'm not sure what you mean by "that you saturate your most-negative value to -2^(B-1)+1, which is the negative of the most positive value +2^(B-1)-1, then you can simply rearrange the real-valued data into a complex-valued data stream." The bandwidth of interest is +/- 3MHz. Also, the channel of interest has a 25KHz BW. I'm thinking once the +/-3MHz is at baseband I can then filtering and FM demodulate the 25KHz channel in the DSP. How do I identify the maximum amount I can decimate by? If I can work how much resources used for this then maybe I can gauge how big FPGA/CPLD I would need. The core processor of the DSP is 400MHz - I think it would be nice to decimate as much as possible to increase the instructions per cycle in the DSP. but as you say decimating "as much as is needed", I can use less resources in the CPLD/FPGA. This will require optimization methods. Do you have any suggestion on selecting a FPGA for the DDC? Many thanks in advance. Cheers, Les.
