Using CPLDs as a dedicated DDC

Create a design and synthesize it in a CPLD. I'm not sure why you are using an NCO though, since it is not necessary.

If you are sampling a real-valued signal at 37.4MSps, then I assume you are sampling DC to 37.4/2 = 18.7MHz, or a Nyquist zone above that.

To mix that signal to complex-valued baseband you can use a complex-valued exponential at fs/4, which is just 1, -j, -1, +j.

Assuming your ADC output format is 2's compliment, and that you saturate your most-negative value to -2^(B-1)+1, which is the negative of the most positive value +2^(B-1)-1, then you can simply rearrange the real-valued data into a complex-valued data stream.

But mixing to complex-valued baseband is only half the DSP task, your real question should be "how much logic does my decimation filter require"? Since you need to low-pass filter that complex-valued data and decimate to create the signal you expect to pass to the DSP (the mixing/filtering/decimation could all be implemented by a single multi-rate filter). The "complexity" and hence resource requirements of that filter depend on how much signal there is in the band you want the DSP to process.

You state above that your signal of interest has a bandwidth of 6MHz, is that +/-6MHz, or +/-3MHz? If its the latter, then you can decimate your signal quite a lot before passing it to the DSP, or you can decimate it "as much as is needed" to get the data onto the DSP. The latter option would have a faster data rate to the DSP, less decimation in the CPLD, and a decimation filter with a slower transition band, hence it would be simple (not too resource intensive). A CPLD might be able to do it, or worst-case a small FPGA. Personally I would recommend a small FPGA, as they have the benefit of on-chip memories, which are useful for the FIFOs needed for bridging across the clock domain from your ADC to your DSP, and also you can use SignalTap to capture ADC samples while debugging.

Cheers,

Dave