Using CPLD/FPGA as a Timer

Hello,

I just was aware, that the said MAX_COUNT overflows the integer range, thus my example is incorrect. Changing the count value to unsigned with full length, the LE consumption increases to 54. Sorry for the confusion.

Frank

-- Modified Quartus II VHDL Template
-- Binary Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic
(
	MAX_COUNT : unsigned(35 downto 0) := x"861C467FF"
);
port
(
	clk	  : in std_logic;
	reset	  : in std_logic;
	enable	  : in std_logic;
	q	  : out std_logic
);
end entity;
architecture rtl of timer is
begin
process (clk)
	variable   cnt	: unsigned(35 downto 0);
begin
	if (rising_edge(clk)) then
		if reset = '1' then
			-- Reset the counter
			cnt := (others => '0');
			q <= '0';
			elsif enable = '1' then
			-- Increment the counter if counting is enabled
			if cnt < MAX_COUNT then			   
				cnt := cnt + 1;
				q <= '0';
			else
				cnt := (others => '0');
				q <= '1';
			end if;
		end if;
	end if;
end process;
end rtl;

P.S.: Rounding MAX_COUNT to x"860000000", the LE consumption decreases to 41