Using CPLD/FPGA as a Timer

Hello,

basically, the simple fact that the system needs (2*3600*5e6) states can't be bypassed. ceil(log2((2*3600*5e6)-1)) = 36 gives the number of bits for a binary counter, which is always the minimal state representation, I think.

Using a modified vhdl binary counter template with a MAX II CPLD, I got an overall LE consumption of 46. The 10 additional LE's are a tribute to the particular MAX_COUNT, a 2**N value would allow a simple ripple-carry counter.

Best regards and Happy New Year!

Frank

-- Modified Quartus II VHDL Template
-- Binary Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic
(
	MIN_COUNT : natural := 0;
	MAX_COUNT : natural := (5e6*3600*2)-1
);
port
(
	clk	  : in std_logic;
	reset	  : in std_logic;
	enable	  : in std_logic;
	q	  : out std_logic
);
end entity;
architecture rtl of timer is
begin
process (clk)
variable   cnt	: integer range MIN_COUNT to MAX_COUNT;
begin
	if (rising_edge(clk)) then
		if reset = '1' then
		-- Reset the counter
			cnt := MIN_COUNT;
			q <= '0';
		elsif enable = '1' then
		-- Increment the counter if counting is enabled
			if cnt < MAX_COUNT then			   
				cnt := cnt + 1;
				q <= '0';
			else
				cnt:=MIN_COUNT;
				q <= '1';
			end if;
		end if;
	end if;
end process;
end rtl;