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Basically, I tried to focus on the original question. Further suggestions may be helpful, of course. I think, however, you should also give some explanation for what you regard as best practise.
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Agreed. Sorry about that. Thanks for clearing up my post. Just a few comments below.
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std_logic_unsigned may be regarded as bad practise. Personally, I dislike it too. But it simply introduces a Verilog-like behaviour in VHDL and may be appropriate for some simple applications. Regarding std_logic_arith, did you notice that all (or most) Altera VHDL IP is using it?
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I do see Altera's IP using it, and I cringe every time I see them used.
On a side note, I don't like how all of their IP ports which are clearly fed with signed or unsigned data don't expose this datatype.
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It's fully legal VHDL code anyway. In an edge sensitive process, a sensitivity doesn't change the behaviour, neither in synthesis nor simulation. (Personally, I would use
process(clock) at least to improve readbility and reserve
wait until for simulation timing.)
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Agreed and understandable. VHDL is extremely versatile, but not necessarily always the easiest to read - so maintaining a clear intent is important when writing code.
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