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While Quartus
may infer a RAM from this code, it's not using best practices.
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It actually
does.
Basically, I tried to focus on the original question. Further suggestions may be helpful, of course. I think, however, you should also give some explanation for what you regard as best practise.
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First, you should be using ieee.numeric_std.all instead of std_logic_arith, and std_logic_unsigned.
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std_logic_unsigned may be regarded as bad practise. Personally, I dislike it too. But it simply introduces a Verilog-like behaviour in VHDL and may be appropriate for some simple applications. Regarding std_logic_arith, did you notice that all (or most) Altera VHDL IP is using it?
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Second, your memory access process should have a sensitivity list and look something like this.
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It's fully legal VHDL code anyway. In an edge sensitive process, a sensitivity doesn't change the behaviour, neither in synthesis nor simulation. (Personally, I would use
process(clock) at least to improve readbility and reserve
wait until for simulation timing.)
As another comment:
after 1 ns is valid in simulation only and ignored in synthesis. And the
rw / memsave logic seems dubious to me, but may serve a purpose anyway.
Honored Contributor
