As far as using JTAG as a programming sequence, that's fine, and I recommend the having the JTAG header, but programming the FPGA this way will not stick, unless you also support some other means of programming. (IE Active Serial, Passive Serial, etc).
IE It will loose the programming at every power cycle unless you program a flash device to hold the programming.
For Systems with an external CPU, we tend to use either passive serial or passive parallel programming mode.
For systems with no CPU we tend to use Active Serial mode. In this case, we have the "Active Serial" header and the JTAG header so we can program the Active serial device directly. This can be bypassed through JTAG, but it's more complicated, to do it that way.
As far as a USB Blaster compatible device, we've had good luck from Terasic's programmer.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=74 Regards,
Pete