USB Blaster and other JTAG devices in chain

hello,

Few more details:

We upload the configuration file to the FPGA through JTAG using the programmer. When we do that, additional two non-Altera devices are well defined (using respective bsdl files).

When we finish programming and test the board, communication with the devices that are attached to the downstream of the PCIe switch fail.

Meaning , communication with few internal parts of the PCIe switch fails. Further investigation revealed, the configuration space registers of the upstream port in the PCIe switch were changed. It happened during the FPGA JTAG configuration upload.

We bypassed the problem by bypassing the CPU/PCIe-switch TDI/TDO (connect TDI to TDO) and by tying the TRST pins of both to GND. This is a temporary solution.

Question remains: how did this FPGA programming affect the PCIe internal registers?

Thank you

Gil Hershman