Have you tryed to connect EMAC through FPGA yet? I've tryed to connect EMAC to the FPGA logic, there make some data changes and route them back to EMAC RX channel. It works but at first, I've problems with data clocking. I connect emac_gtx_clk_out to the emac_rx_clk_in and emac_tx_clk_in but data wasnt benn synchronous with this clock (taken by the Signal Tap). Then I connect emac_gtx_clk_out to the PLL (1:1) and PLL outputs was source for emac_rx_clk_in and emac_tx_clk_in. Then the data leaving EMAC to the FPGA was synchronous with emac_tx_clk_in. Why I need PLL? Is there some documentation with this problematics?
I must add that the EMAC was set from Linux at 1 Gbps. TX works (verified by Signal Tap) but receiving doesn't work (DMA initialization problem in EMAC module).
Thanks
Milan