urjent logarithm implementation

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity logarithm is

Port ( clock : in STD_LOGIC;

ip_bit : in STD_LOGIC_VECTOR (13 downto 0);

log_ot : out STD_LOGIC_vector(13 downto 0));

end logarithm;

architecture Behavioral of logarithm is

component ipcore_arctanh is

Port ( x_ip : in STD_LOGIC_VECTOR (15 downto 0);

y_ip : in STD_LOGIC_VECTOR (15 downto 0);

x_op : out STD_LOGIC_VECTOR (7 downto 0);

clock : in STD_LOGIC);

end component;

component fpdiv is

Port ( diva : in STD_LOGIC_VECTOR (15 downto 0);

divb : in STD_LOGIC_VECTOR (15 downto 0);

---div0 : out STD_LOGIC;

divq : out STD_LOGIC_VECTOR (15 downto 0));

end component;

signal b,q,s,t : integer;

signal l1,l2,l3 : std_logic_vector (15 downto 0);

signal l :std_logic_vector (7 downto 0);

signal p :std_logic_vector (15 downto 0) := "0000000000000001";

begin

l1 <= ip_bit - '1';

l2<= ip_bit +'1';

k1:fpdiv port map (l1,l2,l3);

k2 : ipcore_arctanh port map (p,l3,l,clock);

b <= conv_integer (unsigned(l));

q<= (2*b);

log_ot <= conv_std_logic_vector(q,14);

end Behavioral;

this is my code in vhdl,but in simulation it gives '0' for any input given. is there any logic mistake. plz help.

You said you were looking for an implementation without cores, but you are using two in that code. I don't know how the cores you are using have been configured so it's difficult to know if you are using them properly.

If you are looking for an easy implementation without cores, as Tricky said you should try a look-up table solution instead.