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Altera_Forum
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Honored ContributorURGENT PLEASE FREQUENCY DIVIDER FROM 50MHz to 1Hz
I tried to test my design of 50MHz to 1Hz on the altera board so that it can cover 50,000,000 cycle in 10 sec or 1 sec but not indicating that on the board. I need help on how to make it perform this function on the board. I need an urgent reply. Thanks.
this is the code for my design ENTITY FDIVIDER IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( clk : IN STD_LOGIC; clkout : OUT STD_LOGIC ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END FDIVIDER; -- Architecture Body ARCHITECTURE FDIVIDER_architecture OF FDIVIDER IS BEGIN PROCESS (clk) VARIABLE count : INTEGER RANGE 0 TO 25000000; BEGIN if(clk'event and clk='1') then if(count=25000000)then count:=0; clkout<='0'; else count := count+1; clkout<='1'; END IF; END IF; END PROCESS; END FDIVIDER_architecture;3 Replies
Altera_ForumIt could be a good idea to increase the range of the counter variable to "0 to 50000000"
It won't change anything in Quartus, but you would get an error if you tried to simulate it in Modelsim.- Altera_Forum--- Quote Start ---
--- Quote End --- thanks. its really helpful...thanks again.count := count + 1; if count = 50000000-1 then count := 0; end if; if count <25000000 then clk_out <= '1'; else clk_out <= '0'; end if; - Altera_Forum
count := count + 1; if count = 50000000-1 then count := 0; end if; if count <25000000 then clk_out <= '1'; else clk_out <= '0'; end if;
