URGENT PLEASE FREQUENCY DIVIDER FROM 50MHz to 1Hz

I tried to test my design of 50MHz to 1Hz on the altera board so that it can cover 50,000,000 cycle in 10 sec or 1 sec but not indicating that on the board. I need help on how to make it perform this function on the board. I need an urgent reply. Thanks.

this is the code for my design

ENTITY FDIVIDER IS

-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!

PORT

(

clk : IN STD_LOGIC;

clkout : OUT STD_LOGIC

);

-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END FDIVIDER;

-- Architecture Body

ARCHITECTURE FDIVIDER_architecture OF FDIVIDER IS

BEGIN

PROCESS (clk)

VARIABLE count : INTEGER RANGE 0 TO 25000000;

BEGIN

if(clk'event and clk='1') then

if(count=25000000)then

count:=0;

clkout<='0';

else

count := count+1;

clkout<='1';

END IF;

END IF;

END PROCESS;

END FDIVIDER_architecture;