Updating EPCS with new configuration via FPGA

SFL roadmap:

1. SFL implementation in VHDL:

-- declaration

component SFL PORT ( noe_in : IN STD_LOGIC );

end component;

--instantiation

SFL_inst : SFL PORT MAP ( noe_in => '0');

2. Creation of JAM file

a) convert SOF-file to JIC

b) use Quartus programmer tool to convert JIC to JAM

3. Software side ...depends on your system...

here is just a code snippet showing some JAM wrapper routines for lower level bit banging functions you have to do, anything else is from Altera, an experienced C guy will implement/verify it within a day

...

static BYTE TckLevel=0;

static BYTE TmsLevel=1;

static BYTE TdiLevel=1;

# ifdef FAST_JTAG_PROGRAMMING# define TCK_GPO_BIT (1L<<17)# define TDI_GPO_BIT (1L<<26)# define TDO_GPIO_BIT (1L<<8)# endif

void JamInit(void) {

# ifdef FPGA_EEPROM

UWORD32 u32_low = 0;

UWORD32 u32_high = 1;

bySetDirectionVio(JTAG_TMS, IOCTRL_DIR_OUTPUT_DONTCARE);

# if SDI_OUT_OPTION == SDI_2972

bySetVioBurst(SPI_CS_SDI_OUT, &u32_high, 1);

# endif

// TCK=0

TckLevel=0;

bySetVioBurst(JTAG_TCK, &u32_low, 1);

// TMS=1

TmsLevel=1;

bySetVioBurst(JTAG_TMS, &u32_high, 1);

// TDI=1

TdiLevel=1;

bySetVioBurst(JTAG_TDI, &u32_high, 1);

# endif

}

void JamClose(void) {

# ifdef FPGA_EEPROM

bySetDirectionVio(JTAG_TMS, IOCTRL_DIR_INPUT);

# endif

}

void JamTmsHigh(void) {

# ifdef FPGA_EEPROM

UWORD32 u32_high = 1;

if(TmsLevel != 1) bySetVioBurst(JTAG_TMS, &u32_high, 1);

TmsLevel = 1;

# endif

}

void JamTmsLow(void) {

# ifdef FPGA_EEPROM

UWORD32 u32_low = 0;

if(TmsLevel != 0) bySetVioBurst(JTAG_TMS, &u32_low, 1);

TmsLevel = 0;

# endif

}

void JamTdiHigh(void) {

# ifdef FPGA_EEPROM

# ifdef FAST_JTAG_PROGRAMMING

UWORD32 u32;

if(TdiLevel != 1) {

GET_REG(GP_OUTPUT,u32);

u32 |= TDI_GPO_BIT;

SET_REG(GP_OUTPUT,u32);

}

TdiLevel = 1;

# else

UWORD32 u32_high = 1;

if(TdiLevel != 1) bySetVioBurst(JTAG_TDI, &u32_high, 1);

TdiLevel = 1;

# endif

# endif

}

void JamTdiLow(void) {

# ifdef FPGA_EEPROM

# ifdef FAST_JTAG_PROGRAMMING

UWORD32 u32;

if(TdiLevel != 0) {

GET_REG(GP_OUTPUT,u32);

u32 &= ~TDI_GPO_BIT;

SET_REG(GP_OUTPUT,u32);

}

TdiLevel = 0;

# else

UWORD32 u32_low = 0;

if(TdiLevel != 0) bySetVioBurst(JTAG_TDI, &u32_low, 1);

TdiLevel = 0;

# endif

# endif

}

void JamTckHigh(void) {

# ifdef FPGA_EEPROM

# ifdef FAST_JTAG_PROGRAMMING

UWORD32 u32;

if(TckLevel != 1) {

GET_REG(GP_OUTPUT,u32);

u32 |= TCK_GPO_BIT;

SET_REG(GP_OUTPUT,u32);

}

TckLevel = 1;

# else

UWORD32 u32_high = 1;

if(TckLevel != 1) bySetVioBurst(JTAG_TCK, &u32_high, 1);

TckLevel = 1;

# endif

# endif

}

void JamTckLow(void) {

# ifdef FPGA_EEPROM

# ifdef FAST_JTAG_PROGRAMMING

UWORD32 u32;

if(TckLevel != 0) {

GET_REG(GP_OUTPUT,u32);

u32 &= ~TCK_GPO_BIT;

SET_REG(GP_OUTPUT,u32);

}

TckLevel = 0;

# else

UWORD32 u32_low = 0;

if(TckLevel != 0) bySetVioBurst(JTAG_TCK, &u32_low, 1);

TckLevel = 0;

# endif

# endif

}

int JamTdoRead(void) {

# ifdef FPGA_EEPROM

# ifdef FAST_JTAG_PROGRAMMING

UWORD32 u32_1, u32_2;

do {

GET_REG(GPIO_EXT_PORTA,u32_1);

GET_REG(GPIO_EXT_PORTA,u32_2);

} while(u32_1 != u32_2);

if(u32_1 & TDO_GPIO_BIT) return 1;

else return 0;

# else

UWORD32 u32_res;

byGetVioBurst(JTAG_TDO, &u32_res, 1);

if(u32_res) return 1;

else return 0;

# endif

# endif

}