Unused IO Banks

--- Quote Start ---

im using the EP1C3T100C8N, but only actually using 14 IO pins so two banks are unused

--- Quote End ---

p253 has the statement I recall:

http://www.altera.com/literature/hb/cyc/cyc_c5v1.pdf

"Normal operation does not occur until both power supplies are in their

recommended operating range"

--- Quote Start ---

I think i will power the other two banks any way, im not saving any thing by not powering them just a little bit extra routing lol

--- Quote End ---

That would be my advice.

Cheers,

Dave

im using the EP1C3T100C8N, but only actually using 14 IO pins so two banks are unused

I think i will power the other two banks any way, im not saving any thing by not powering them just a little bit extra routing lol

thanks for your reply :)

--- Quote Start ---

If im not using any pins on a IO Bank do i need to connect up its IO VCC? or can i leave this bank completely un powered?

--- Quote End ---

Which device are you using?

FPGAs have a power-on-reset that will not release until the power rails are all within tolerance.

I'm not sure what flexibility there is in not having some VCCIO banks power up.

If you read the handbook and cannot quite figure it out, you could always start removing power from VCCIO banks on a development board and see if the FPGA still works. Eg., the Terasic DE-115 has VCCIO jumpers on some of its banks, while other boards have resistors between their main power rails and the VCCIO banks.

Cheers,

Dave