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Just to update you, Dave. The problem was indeed that the unused pins were set to "as outputs driving ground". When I changed it to "tristate inputs with weak pull up" the voltage went back to 3.3V.
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Great!
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I have the data transferring now and I've also modified the code to use the 8 MHz global clock instead of relying on SCK, as it was before in my old design.
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If I was going to resynchronize an SPI clock to a local clock, I would instead write the code as:
1) SPI SCK goes through a dual DFF synchronizer. SPI select also needs to be synchronized. MISO and MOSI do not.
2) Generate a pulse on the rising or falling edges (or both since you want to read on rising and shift out on falling). The edge detector can be built by delaying the synchronizer output by one clock, and then using the delayed and non-delays signals (I'll let you figure it out).
3) Your SPI controller FSM can then be clocked at 8MHz, with inputs spi_sel, spi_sck_rising and spi_sck_falling to indicate edges.
You can then use those controls to determine whether your command shift register is shifted (on rising-edges), or your response is shifted (on falling-edges).
Write a testbench to generate the SPI input waveforms and you'll start to see what I mean.
Cheers,
Dave
Honored Contributor
