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Altera_Forum's avatar
Altera_Forum
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9 years ago

Unregistered M9K block inputs? Cyclone-3

I created dual-port RAM, and ports data, address and wren are registered. At different points in time I need to have different addresses at address lines (of course). I use register for it, writing address to it, and connecting it to registered address input of M9K. Clock used is the same for register and RAM. With this circuit I have two cycles of delay - first is latch address to register, then latch from this register to register of M9K block, and only next cycle I have required data.

Is there any way to reduce number of cycles? If I would be able to write directly to registered input of the RAM... Or disable registers at M9K input. Probably it is possible, please tech me if there's a way. Thank you.

Edit: having clock negated at the RAM is not an option. Clock cycle is 8.8 ns, and half of it if using negated clock is 4.4 ns. I empirically proven that while it works with 8-bit data width, it does not work properly with 16-bit data width - data being read is partially corrupt (I can not explain it and do not know the cause why it is this way). Thus minimal applied read/write interval should be full clock cycle, 8.8 ns.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    You can remove the registers on output port 'q'. When you configure the ram, on the 'Regs/Clkens/Aclrs' tab, uncheck the "Read output port(s) 'q'" checkbox under "Which ports should be registered?"

    This will reduce the number of cycles to one. This comes at a cost - your ram won't run as fast as would with the register. However, that may be fine for your design.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I think he's saying he already turned off the output registers. He's latching the address external to the RAM (delay 1) and then the address is registered at the RAM input (delay 2).

    eugeny - If I interpreted your post correctly then there is no way to reduce the delay because you cannot remove the RAM input registers. You'll just have to find a way to work around it. Write latency is usually not a problem, but read latency can be a pain to deal with depending on how the RAM is used. Be creative - you'll find a way.

    Bob
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    If I have misinterpreted your first post, and you've already switched the output register off, then the only way you can save a cycle is to use a combinatorial input to your address register.

    --- Quote Start ---

    I need to have different addresses at address lines (of course). I use register for it

    --- Quote End ---

    You don't need to use a register for this - unless you need to read it's value. If you do, then I suggest you implement a duplicate of the registered address and read from that. The duplicate register will contain the same value at the address registers (that's inside the RAM IP) but you'll be able to read them and use the value in your calculation - if you need to. So, you should be able to save one cycle.

    As rsefton states - there's no way to remove the input registers. If you want a truly 'zero cycle' RAM you'll have to implement it in logic.

    Cheers,

    Alex