Honored Contributor
Honored ContributorYou never got a response to this so I'll chime in ...
It should not be possible to get a 90 degree phase difference between the output clocks given your circuit. The delay between the clocks in the oscilloscope trace is only about 2ns. I'm guessing that's just differences in the routing paths from the ROM through the fabric to the output pins. 2ns seems like a large difference just due to routing, but if you constrain the output paths, or reclock the sma outputs with output_clk and place those registers in the IOBs, then you should see the phase difference disappear. Have you already resolved this for yourself? If so, please post back what you found.
