unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi

I'm sorry that I confused you. Actually it was always Pin R7 I talked about. We use this user output as Backlight-Enable signal in our design.

The picture I attached, shows that this output R7 (trace C3) is going low (instead high with weak pull-up) in the programming phase when the configuration memory gets accessed via JTAG-SFL-ASMI. Visible because the Chipselect ouput 'CSO' of the FPGA (trace C2) is toggling.

Before this phase of programming you can see that the output is high with weak pull-up. Which is as expected and I assume that this is the phase where the SFL bridge gets loaded to the FPGA via JTAG.

At the beginn and at the end of the picture the output is high, when the FPGA is in user mode.

Trace C1 is the CONF_DONE output of the FPGA.

So, my question. Way gets the user output R7 low during programming?

Regards

Fredi