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Altera_Forum
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13 years ago

undesired sidebands on Cyclone IV E PLL output

I am using a PLL in a Cyclone IV E. I have a 20 MHz oscillator connected to a clock-input pin. I am trying to get 200 MHz as the output. For the design, I am using only an ALTPLL megafunction bloc...
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Altera_Forum
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13 years ago

That is a tough one to figure out, because that is out of the normal for the LDO. This is also another reason why I often debate on using a chip such as the Lattice power manager series of chips, and qualifying all the voltage rails before allowing connection downstream. This adds cost and complexity to the board, but the larger the $ of the FPGA, the more and more valuable such a protection scheme takes on value. -James