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Honored ContributorUnderstanding training patterns for Stratix-II deserializer DPA
Hi,
I am trying to figure out requirements for Dynamic Phase Alignment (DPA) as implemented by LVDS receiver (non-GXB) in Altera Stratix-II family. The device handbook provides very limited information: "the dpa block requires a training pattern and a training sequence of at least 256 repetitions of the training pattern. the training pattern is not fixed, so you can use any training pattern with at least one transition on each channel." I want to know a bit more than that. In particular: 1. Minimal training pattern length in bits 2. Maximal training pattern length in bits 3. Does Minimal/Maximal length depend on deserialization factor? 4. Are there limitations for minimal/maximal transition density? Did you, dear experts, see more detailed information on the issue or, may be, learned something about it from experience? Best Regards, Michael13 Replies
Altera_ForumI believe DPA run length is the max number of cycles of a constant value can occur before loosing lock. As for a training pattern, I've heard pretty much anything with transitions will work, but with fewer transititons it may just take longer. It is not looking for a pattern though(such as 10-bit comma), just transitions to figure out where the data changes and where to center the clock. There is no word alignment occuring, as that has to be done by you.
- Altera_Forum--- Quote Start --- In the last section of the handbook(all the timing numbers) there should be DPA specs. --- Quote End --- There are specs in Chapter 5, but they don't answer my questions. For example, could long run of 10-bit "comma" patterns generated by one of the popular 8b/10b alphabets serve as DPA training sequence when deserialization factor=8 rather than 10? Chapter 5 gives no answer. To the contrary, the spec tables in Chapter 5 introduce yet another concept that I don't understand (and that handbook does not explain) - DPA run length. If there is no good answer to my questions above, may be, somebody here could answer a related question. What happens when DPA is presented with sequence of bits that is guaranteed to have certain density of transitions, for example, >10%, but is totally aperiodic? Does DPA do nothing at all in this case or does it continue to track after timing changes, just less efficiently than with "legal" training sequence?
- Altera_Forum
In the last section of the handbook(all the timing numbers) there should be DPA specs.
