Understanding Clocks for Arria II

There's no minimum clock frequency for the FPGA; only for the PLLs (and transceivers).

As for maximum clock frequency, it's a bit more complicated.

I think the FPGA input clock pins will accept clocks up to 500 MHz, but only with differential I/O standards. With single ended (ie, LVCMOS), the maximum frequency will be lower.

And the maximum frequency at which your design will be able to operate will depend on your design and on the FPGA's speed grade.

What you need to do is to synthesize your design (with I/O assignments) and see the timing report.

If you don't have a prototype of your design, try to create a simple mock up.