Understanding Clocks for Arria II

What you really need is to read chapter 5: Clock Networks and PLLs in Arria II devices.

But to get you started:

The FPGA has a number of clock input pins; each clock input pins can drive a few GCLK networks; ANY of the GCLK networks can drive logic all over the chip.

So, if all you need is one clock and no PLLs, you just need to connect your clock to one of the clock input signals.

Each clock input pin can also drive two PLLs (see table 5-6 and 5-7).

If you only want to use up to two PLLs and you don't care about which ones, then you need to do no more than above.

If you want to use more than 2 PLLs or you care about which PLLs you'll use, then you'll have to look into table 5-6 or 5-7 and connect your clock signal to more than one clock input pin.

Or you can just connect your clock signal to every clock input pin. It also works well.

Then you have the transceivers. If you want to use those, you'll need to provide clocks though the transceivers clock input pins.

Read the Transceiver Clocking chapter for that part.