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Based on the above I put together a simple two way set associative instruction cache with 4Kb internal memory and it works in the simulator with a simple test toplevel entity but now I need to check how I can simulate this after I set it up in a qsys system.
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After you get this packaged into a Qsys component with a _hw.tcl file, what you want to do is to get a simulation going with the Avalon BFM's Search on here for "BFM" and you'll find threads and examples.
https://www.altera.com/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html
Honored Contributor
