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Altera_Forum
Honored Contributor
8 years agoUnconstrained paths in timequest result in setup violation
Hi, I have a code which I am using in Qsys. The ports are reported in unconstrained paths in Timequest. What is the best way to eliminate them? I have a clean timing before constraining these p...
Altera_Forum
Honored Contributor
8 years agoYou should not set output delays to 0. You need a range of delay (that's why it's called min and max) that defines the external delays to meet setup and hold timing at the output ("downstream") device. Check out this online training to learn how to calculate the values for set_output_delay:
https://www.altera.com/support/training/course/odsw1118.html