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Altera_Forum
Honored Contributor
8 years agoUnconstrained paths in timequest result in setup violation
Hi, I have a code which I am using in Qsys. The ports are reported in unconstrained paths in Timequest. What is the best way to eliminate them? I have a clean timing before constraining these p...
Altera_Forum
Honored Contributor
8 years agoHi Kaz,
I have tried doing them. When I have a constraint on (output ports) output delay min and max of 0, I have a negative slack of -1.5. Is there any option how can I correct the same?