Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorUnconstrained paths in timequest result in setup violation
Hi, I have a code which I am using in Qsys. The ports are reported in unconstrained paths in Timequest. What is the best way to eliminate them? I have a clean timing before constraining these p...
Altera_ForumHonored Contributor
Honored ContributorYou need first correct constraints then pass timing. There is no point passing timing when constraints don't exist or are wrong (that will be false pass).
io timing is your domain of design and depends on board delays of clock and data and the way it is sampled in or out. if such ports are irrelevant you can relax the constraints on them.
