unable to merge fast pll error

Hi all,

i have a very difficult error, which as i see, Altera cant solve or point to the problem.

this is very troubling to us, and puts all the project at risk.

the project was minimize to this basic configurations:

1. 2 XTSE connected to PCSs (each TSE have its own PCS).

2. TSE + pcs, 3rd party ip + PCS.

the 3rd part ip don't use any PLL.

while compiling option 1, all ok.

while compiling option 2 - error that Quartus cant merge PLL therefore unable to fit design.

can anyone help here??