Forum Discussion
Altera_Forum
Honored Contributor
13 years ago1) Yes, the master is configured in active serial mode, and declares the EPCS64 as the EPROM device
2) The Stratix is configured in passive serial mode. 3) the DCLOCK and DATA0 signal get to the proper pins in bothFPGA devices, and the quality of the signals as probed with a scope and a FET probe is excellent. 4) the chaining from the master to slave (nCEO to nCE) was also checked with the scope and occurs as expected. I have used this kind of configuration in the past without any problem with Cyclone devices. But it is the first time I use a Stratix as a slave device, and a Cyclone as the master. Any more hints? Thanks again for the advice.