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As you are using raw ethernet, one way to do that could be to use a special Ethertype value for your packets. Then you can use a component similar to the UDP port to channel mapper, but that would read the Ethertype instead of the UDP port number. If it is your custom Ethertypem, redirect the packet to your custom component, and if not redirect it to the Nios system.
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Hi Daixiwen,
Thanks for the Idea.
Writing Hard core Verilog code for the custom component which read Ethertype and direct the packet according to that seems difficult for me.
To make myself easy I proceeded in following way:
I took only one channel out of 4 of "UDP offload example" (see attachment) and do the UDP instead of raw ethernet at first to make sure if this works for my DE2-115 board (Cyclone IVE with Quartus 12.1 having Qsys instead of SOPC) or not.
if it works then I can switch to raw ethernet later.
Yesterday, I tried this(see attachment) and it was successfully generated with Qsys and also successfully compiled with Quartus but had time constraint problem(screenshot in attachment).
how to fix this time constraint?
When I looked into UDP offload example (software side), there is _sw.tcl file (similar to _hw.tcl file for hardware custom component in Qsys) for most of the custom component. Internet says: it is software driver for all custom component and generated as board support package by NIOS software build tool Eclipse. I didn't understand it clearly.
There are also C program for every custom component. Does it mean software programming is also needed for every custom component for this project along with hardware programming?
one more thing how can I debug Custom component added in Qsys whether it is working or not?
In short what could be the next step?
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