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Altera_Forum
Honored Contributor
14 years agoUART Transmitter Sends Bytes Out of Order
Hello, I have the following Verilog code which sends 8 bytes to the serial port successively after a button is pressed. The problem is, the bytes are sent out of order as to what I would e...
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- In the first piece of code (the not working one) in SEND_BYTES state you wrote: tbyte = plain_text[byteN*8 +: 8]; What does that mean? I have never seen such a syntax. Is this a typo? I'd rather used: tbyte = plain_text[(byteN+1)*8: byteN*8]; --- Quote End --- Check section 4.2.1 of the 1364-2001 spec, Vector bit-select and part-select addressing fe, if you declare a reg as: reg [15:0] d, then d[0 +: 8] is equivalent to d[7:0] if you declare it as: reg [0:15] d, then d[0 +: 8] is equivalent to d[0:7] there is also a -: operator that works similarly As for the question in hand, you should get a simulator (there are free ones), and check your timing constraints