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Altera_Forum's avatar
Altera_Forum
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11 years ago

UART, SPI, I2C buffer/FIFO in Qsys

Hi to everybody,

is there the possibility to have a FIFO buffer on UART, SPI and I2C peripherals in a Qsys system for FPGA MAX 10?

My peripherals should write the received data (one or more Byte) in this buffer and the master (cpu component) should read this data before the buffer is full.

Viceversa, when the cpu component has data to write (typically more than one Byte), it should write in this buffer and then the peripherals should read and transmit the data.

I've read about Avalon-ST Single-Clock FIFO, Avalon-ST DUAL-Clock FIFO and Avalon FIFO Memory but I didn't understand much.

Am I on the right way or perhaps do I have to use a DMA controller? How can I connect in Qsys these FIFO/DMA on the peripherals mentioned above?

Anybody can help me?

Thanks in advance.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    I've tried to use DMA Controller without FIFO to read 10Bytes from On-chip Memory and write them on SPI Controller.

    The SPI Controller hasn't flow control (in spite of on the datahseet it seems it has it) hence the DMA Controller continues to wirte Byte toward the SPI Controller without to wait the actual transmisson of the Byte on the MOSI output (the DMA writes Byte continuously). For this, the system is not good for my purpose.

    Then I used another Nios processor and a FIFO to handle the communication: the main Nios processor writes into the FIFO and the second Nios processor as soon sees a Byte in FIFO and the TRDY flag is 1 (the SPI Controller tx register is ready to accept another data), it retrieves the Byte and transmits it toward the SPI Controller.

    The second Nios processor has a main() function very simple, without interrupts: basically it checks if the FIFO contains data and if the TRDY flag is 1 and if so, it retrieves the byte and transmits it toward the SPI Controller tx register.

    Viceversa, when the SPI receives something, it rises the RRDY flag to 1 and the second processor read the rxdata register of the SPI Controller and put the Byte in the same FIFO (the same FIFO because my communication is half duplex, if you want a full duplex communication you have to use 2 FIFO for the SPI, one for TX and one for RX).

    In this way the main processor has to write/read to/from the FIFO only and the second processor polls the FIFO/SPI Controller, that is it reads from FIFO and writes to SPI Controller or viceversa.

    This second processor could be used even to do same things with I2C or UART.

    It could be a Nios/e (economy) processor if the datarate of your communication is not too high (1Mbps) because the Nios/e uses 6 clock cycles for instruction. Otherwise you have to use a Nios/f processor. For example i use the latter processor because my SPI comunication is at 10Mbps.

    This is my solution. If anyone has one better, please tell it me.

    Bye.