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Honored Contributor
Honored ContributorUART recive and send loop
hi: I post attachments about the UART recive and send loop HDL code ( attachments 1)and signaltap waves . I have some questions to ask your gurus~! 1:I use the 50M oscilation, w...
Altera_ForumHonored Contributor
Honored ContributorRegarding question 2, I think a major issue is the fact you use baud_clk and baud_clk16 as clocks signals for the send and recv processes. These are actually generated signals and they don't have the low skew requirement as a real clock has (e.g. from a pll).
You should clock every process with the primary clock CLK and you'd rather generate single clock enables at the baud_clk and baud_clk16 frequencies to make your job.
