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Shoval
New Contributor
New ContributorUART 16550 compatible Linux device
Hello all, In my Quartus project I connected a UART 16550 compatible soft IP, and it is visible in the .sopcinfo generated. Later I build a .dtsi and a .dtb files using yocto angsrom, in the .dtsi ...
aikeu
Regular Contributor
Regular ContributorHi Shoval,
I missed out the part which referring to the 16550 ip when browsing through the nodes.
May I know the exact address which the 16550 soft ip is pointing in the qsys design?
From the below, I am seeing the address is directly pointing to 0x00000000 :
a_16550_uart_0: serial@0x000000000
Thanks.
Regards,
Aik Eu
ShovalNew Contributor
New ContributorHi,
The address of the IP is 0xc0000000, its base address is 0xc0000000 under "hps_0_bridges" with an addresss offset of 0x00000000.
as you can see from the .dtsi file below:
########
hps_0_bridges: bridge@0xc0000000 {
compatible = "altr,bridge-18.1", "simple-bus";
reg = <0xc0000000 0x20000000>,
<0xff200000 0x00200000>;
reg-names = "axi_h2f", "axi_h2f_lw";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0xc0000000 0x00000200>,
<0x00000001 0x00020000 0xff220000 0x00000008>,
<0x00000001 0x00020010 0xff220010 0x00000008>;
a_16550_uart_0: serial@0x000000000 {
compatible = "altr,altera_16550_uart-18.1", "altr,16550-FIFO128", "ns16550a";
reg = <0x00000000 0x00000000 0x00000200>;
interrupt-parent = <&hps_0_arm_gic_0>;
interrupts = <0 40 4>;
clock-frequency = <100000000>; /* embeddedsw.dts.params.clock-frequency type NUMBER */
fifo-size = <128>; /* embeddedsw.dts.params.fifo-size type NUMBER */
reg-io-width = <4>; /* embeddedsw.dts.params.reg-io-width type NUMBER */
reg-shift = <2>; /* embeddedsw.dts.params.reg-shift type NUMBER */
}; //end serial@0x000000000 (a_16550_uart_0)
######
Attached is the .dtsi file, under line 99 is the hps_0_bridge node instance and under line 110 is the 16550 UART node instance.
(suffix changed to .txt for upload purposes)
