type of identifier "clock" does not agree

Hi everyone,

I have a problem due to the type of identifier "clock" as I declare as a bit type. Below is my short code:

----------------------------------------------------------------------------------------------

Package my_main_data is

Type main_vector is array (7 downto 0) of integer;

End my_main_data;

LIBRARY ieee;

USE ieee.ALL;

Use work.my_main_data.all;

Use work.my_data_types.all;

ENTITY case IS

PORT (

clock : IN bit;

Ip : IN main_vector;

Op : OUT main_vector

);

END case;

ARCHITECTURE case OF case IS

COMPONENT cone

PORT (

I: IN vector;

clk: IN bit;

O: OUT vector

);

END COMPONENT;

SIGNAL out_r1, out_r2: vector;

SIGNAL clk : bit;

BEGIN

R1: cone

PORT MAP (Ip(0), clock, out_r1(0);

PORT MAP (Ip(1), clock, out_r2(0);

End case;

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This error occur when I compile the code:

Error (10476): VHDL error at haar.vhd(62): type of identifier "clock" does not agree with its usage as "integer" type

Can anyone tell me where is my mistake..http://www.edaboard.com/images/smilies/icon_sad.gif Many thanks