Forum Discussion

JCarr18's avatar
JCarr18
Icon for New Contributor rankNew Contributor
7 years ago

type mismatch for generic 'integer_values' (Mixed language design)

Hello, I have a mixed-language design where I would like to instantiate a VHDL module in a Verilog file. The module has the following definition: entity vhdl_module is generic ( integer_values: w...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Javi, Please create new System Verilog HDL file & copy& paste the current .v file in to it as below, File-> New -> System Verilog HDL File. You can use "Save as.." option & remove the .v file from the project. module instantiation will be same as Verilog. Regards, Vikas
  • JCarr18's avatar
    JCarr18
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi @Vicky​ ,

    thanks for your reply. I tried that solution but I got the same error. I guess the conversion I am trying to achieve is not supported so I am thinking about a different solution... How could I pass a single integer from Verilog to a VHDL module? would it be as simplre as for example ".integer_param(5)"? then I could modify my VHDL block to get all the integer parameters separately.

    Thanks again,

    Javi