Altera_Forum
Honored Contributor
12 years agoTSW1400 (Stratix IV) Starting Out
Hello all!
I recent tsw1400 evm (http://www.ti.com/tool/tsw1400evm) from TI, an evaluation board by TI that features a Stratix IV. To begin, I began working off of the application note here (http://www.ti.com/tool/tida-00069), using Quartus II. The application example takes a signal in to an ADC, passes it to the FPGA and into a FIFO, and then back out to a DAC. For my purposes, I have simplified this system. I have stripped this down to a simple counter, ROM, and a DDR Converter (ALTDIDO_TX from the example). In the default configuration, you cannot configure the TSW1400 over JTAG, but you can over USB (technically also JTAG) as seen in this thread (http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/255540.aspx?pi79999=1), using the TI HSDC Pro software. When I download the firmware to the board using the process here, I get the error shown in this thread (http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/265659.aspx) (indicating nothing, really). However, at this point, I'm simply trying to verify that the code had made it to the board. To do so, I added this to the end of the Top Level:
assign led = 1'b1;
assign led = 1'b1;
assign led = 1'b0;
assign led = 1'b0;
assign led = 1'b1;
assign led = 1'b1;
assign led = 1'b0;
assign led = 1'b1; Note, these are just random 1's and 0's so I can see if the pattern shows up. Once I compile and create the programming file (.rbf) and upload to the board, I don't get any LEDs lighting up. I'm trying to figure out if there is an issue with my code, or an issue uploading the firmware to the board. The pins should be set up correctly, as I am using the exact configuration from TI, unaltered. I do get a warning (not an error) about some of the outputs being tied directly to GND or VDD when I compile, but the RTL simulation does have the LEDs at the proper logic level. Can someone point me in the right direction? I've attached my top level, but can attach the whole project if necessary.