Thanks a lot Gris72,
I've recheck the project again, you mentioned a good point about unconstraint input/output.
The main code have problem with the following section, it is related to the Ethernet 0, and 1.
nios_system u0(
.clk_clk (sys_clk), // clk.clk
.reset_reset_n (core_reset_n), // reset.reset_n
.tse_mac_conduit_connection_rx_control (NET1_RX_DV), // tse_mac_conduit.rx_control
.tse_mac_conduit_connection_rx_clk (NET1_RX_CLK), // .rx_clk
.tse_mac_conduit_connection_tx_control (NET1_TX_EN), // .tx_control
.tse_mac_conduit_connection_tx_clk (tx_clk), // .tx_clk
.tse_mac_conduit_connection_rgmii_out (NET1_TX_DATA), // .rgmii_out
.tse_mac_conduit_connection_rgmii_in (NET1_RX_DATA), // .rgmii_in
.tse_mac_conduit_connection_ena_10 (ena_10), // .ena_10
.tse_mac_conduit_connection_eth_mode (eth_mode), // .eth_mode
.tse_mac_conduit_connection_mdio_in (mdio_in), // .mdio_in
.tse_mac_conduit_connection_mdio_out (mdio_out), // .mdio_out
.tse_mac_conduit_connection_mdc (mdc), // .mdc
.tse_mac_conduit_connection_mdio_oen (mdio_oen) // .mdio_oen
);
What do you think the wrong on this code, is it not connected to (sopc/qsys)? or there might be some problem with the clock?