TSE SDC constraint problem

hi,

I use to two TSE ip core in my project, and both in MII/GMII mode. I add SDC file generated by ip core to the project, and i follow a article in altera Wiki to revise the modifiable constraints part in SDC according to my project .

http://www.alterawiki.com/wiki/altera_triple-speed_ethernet_timing_contraints_design_example

I revised as follows:

set SYSTEM_PATH_PREFIX ""

set TSE_CLOCK_FREQUENCY "125 MHz"

set FIFO_CLOCK_FREQUENCY "125 MHz"

set DEFAULT_SYSTEM_CLOCK_SPEED "100 MHz" # name the clocks that will be coming into the tse core named changed from top level

set TX_CLK "phy_a_tx_clk"

set RX_CLK "phy_a_rx_clk"

set CLK "upll25|altpll_component|auto_generated|pll1|clk[2]"

set FF_TX_CLK "upll25|altpll_component|auto_generated|pll1|clk[3]"

set FF_RX_CLK "upll25|altpll_component|auto_generated|pll1|clk[3]"

After recompile the whole project ,i found phy link leds active correctly,by messages printed by nios and signaltap i found the project receive ethernet packet and nios respoding that , and see the RX/TX lights activate appropriately. but on my PC I don't see any respoding packet by Wireshark . And this phenomenon accurd sometimes, accasionally the project work well.

I want to know if the pin of the Marvell 88E111 phy should constrain and how to constrain them:(