Forum Discussion
Trying to reach an EPCQ128A thought Cyclone V dedicated pins, after FPGA loaded in FPPx32
Hello.
Considering the configuration in the table below.
| FPGA/HPS | 5CSXFC6D6F31I7 |
| EPCQ | EPCQ128A |
| MSEL | 0b01010 (FPPx32) |
| GSFI CSR addr | 0xC0010000 |
- Configuration
- HPS boot from µSD, loading a U-Boot
- HPS configures a FPGA design containing a Generic Serial Flash Interface (GSFI)
- HPS asserts 'Bridge enable" command
- EPCQ routed on the AS FPGA dedicated pins
- EPCQ/FPGA routage verification
- We firstly tried to test this connection using a Read ID command asseted on the GSFI CSR throughout the H2F-AXI in 0xC0000000 + 0x00010000 and we get the EPCQ ID 0xFF (Expected 0x18)
- Once we will succes in the read ID command, we will proceed to a write command to set our own value, and then read it back to check the commands execution.
- We will repeat several times following a defined scheme.
Is there a way to boot in FPPx32 and then, while in user mode, drive the EPCQ as a master without MSEL modification ?
3 Replies
- FakhrulA_altera
Regular Contributor
Hi AMass,
From my understanding, yes, you can keep MSEL at FPPx32 and access the EPCQ128A in user mode, but not via the HPS GSFI on the AS‑dedicated pins. Those pins aren’t driven by GSFI, which is why RDID returns 0xFF.Recommended approach:
- Keep MSEL=0b01010 (FPPx32).
- Instantiate the ASMI Parallel II IP in the FPGA and expose it to HPS via H2F/H2F‑Lite to read/write the EPCQ.
- Enable user‑mode access to the AS interface in Quartus (Device and Pin Options).
- Ensure only one master drives the flash; keep WP# and HOLD# high.
If you prefer to use GSFI, the flash must be routed to regular FPGA I/O (or use the HPS QSPI controller).
Regards,
Fakhrul- AMass
New Contributor
Hello.
We will try this solution using this ASMI Parallel II IP soon.
Thanks for your reply.
- JohnT_Altera
Regular Contributor
Hi,
It is not possible. you will need to have the FPGA booted as AS mode in order for you to access the EPCQ in user mode. If you are booting the FPGA in FPPx32 mode then you will not able to access the EPCQ through AS dedicated pin.