Trying to reach an EPCQ128A thought Cyclone V dedicated pins, after FPGA loaded in FPPx32

• Configuration
  • HPS boot from µSD, loading a U-Boot
  • HPS configures a FPGA design containing a Generic Serial Flash Interface (GSFI) 
  • HPS asserts 'Bridge enable" command
  • EPCQ routed on the AS FPGA dedicated pins
• EPCQ/FPGA routage verification
  • We firstly tried to test this connection using a Read ID command asseted on the GSFI CSR throughout the H2F-AXI in 0xC0000000 + 0x00010000 and we get the EPCQ ID 0xFF (Expected 0x18)
  • Once we will succes in the read ID command, we will proceed to a write command to set our own value, and then read it back to check the commands execution.
  • We will repeat several times following a defined scheme.

Is there a way to boot in FPPx32 and then, while in user mode, drive the EPCQ as a master without MSEL modification ?