Trying to develop my own Cordic core at VHDL.. problems

for the rom - take the clock into the separate modules and make the process inside the modules sensitive to clock in the normal way.

For your second issue, to solve the latch problem you need to do what I said, you need to make sure every signal is given an output in EVERY branch AND you put ALL the signals (that are used to assign other signals) in the sensitivity list. This will probably completly change the behaviour you've seen in simulation, but it will reflect what will happen on the real chip.

As for meely/more, it will still be a moore state machine if you clock it - its just delayed by 1 clock cycle. But it will actually work like you intended (and simulation will match hardware). And you wont have to put every signal in every branch.