Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Trouble with EMAC on CycloneV SoC

Hello. We use 5CSEBA4U19I7 chip in our devices. And we have a trouble with EMAC. "EMAC0 pin" in Qsys is configured as "FPGA" mode. GMII signals of HPS instance (emac0_phy_txd_o and em...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

Yup, INI file is required in this case. [..]

--- Quote End ---

Hm okay, thanks. Still strange that the QSYS generated SDC file (*_fpga_interfaces.sdc) creates a clock constraint that depends on an undocumented INI 'hack'. Also there seems to be a lot more needed if one wants to integrate a 10/100/1000Mbit PHY by use of FPGA pins.

The SDC file (soc_system_timing.sdc) contained in the SGMII design example ( http://releases.rocketboards.org/release/2014.11/cv-sgmii-ed/hw/cv_soc_sgmii_ed.tar.gz ) seems to be much more comprehensive, but still painful to replicate.

Pity QSYS is not (yet) able to take the board and PHY related delay parameters and automatically generate the needed timing constraints (as it is e.g. done for DDR RAM).