Trouble with EMAC on CycloneV SoC

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I'm attempting to do this but the constraint is being ignored (~internal_clock could not be matched).

Is there a problem with the HPS timing model?

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The linked example design (Cyclone V RGMII Example Design) contains a very subtle pointer:

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An INI file is required to enable the internal timing path from HPS clock mux.

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Unfortunately, this INI file is missing in the design archive.

I think a 'quartus.ini' file in the project directory is meant and its contents should be

b2t_enable_hps_emac_internal_clock_arcs = on

otherwise {*|fpga_interfaces|peripheral_emac0~internal_clock } is not available and any timing constraint based on it will fail.

On a side note: I am using the latest available Quartus version (15.0 update 2).