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Altera_Forum
Honored Contributor
Honored Contributortri-state input in FSM
Hello, I have built a FSM that has a shared bidir bus as an input and output. The problem that I have is that I continuously have to check the bus if it addresses me and sometimes it goes into...
Altera_ForumHonored Contributor
Honored ContributorIn the first place, you should think about a design that works reliable in real hardware. Secondly care for consistent simulation.
Constructs like if (bus == 16'dzz) aren't synthesizable and thus don't help to create reliable design operation. If high 'Z' happens in real FPGA hardware, the FSM will jump to any of the available next states. This unpredictable behaviour is marked by a 'X' in simulation. There is no chance to get a consistent simulation in this case. Only an unconditional transition, e.g. a reset can recover a known FSM state. The said safe FSM encoding doesn't help here. Also registering the input signal will result in a 'X' state during high Z.
